(1) Field of the Invention
This invention relates to a layout structure for standard cell or library circuit cells which reduce fluctuations in power supply voltage supplied to the cells due to large current swings.
(2) Description of the Related Art
Power and ground voltages are typically supplied to integrated circuit devices by power buses. Frequently the current fluctuations in these buses, caused by circuit switching, cause fluctuations in the voltage actually delivered to the devices. A number of workers have described methods to minimize the fluctuations in the power supply voltage actually delivered to these devices due to current fluctuations in the power supply buses.
U.S. Pat. No. 4,811,237 to Putatunda et al. describe an integrated circuit chip layout arrangement using an interlocking power bus mesh structure.
U.S. Pat. No. 5,391,900 to Onodera et al. describe an integrated circuit chip design having at least one power supply point for supplying electrical power and at least one first, second, and third power trunk line.
U.S. Pat. No. 5,442,206 to Ienaga et al. describes a layout structure of power source potential lines and grand potential lines for integrated circuits which avoids short circuit of lines, uses automated layout design, and avoids the need for manual modification of power source lines.
U.S. Pat. No. 5,537,328 to Ito describes a method of laying out power supply wiring conductors in integrated circuits.
U.S. Pat. No. 5,726,904 to Lin et al. describes power buses having power slits and a method of forming these power buses.
U.S. Pat. No. 6,091,090 to Gheewala describes a layout structure for routing local and global interconnections for a gate array integrated circuit wherein basic cells are arranged as an array having rows and columns.